Apparatus and method of clock recovery for sampling analog signals

ABSTRACT

A clock and phase detect algorithm detects the best sample result for back-end system to recover the sample clock from front-end system. The algorithm of the present invention gets the sample result from ADC by applying slope variation sum (SPVS), which is used in turning points of sample result. The exact sample clock will always get the maximum SPVS value no matter how special or difficult the pattern is. It can detect not only most of normal patterns, but also the special patterns like block, linear piece pattern. The use of SPVS result allows back-end systems to distinguish which clock is the exact clock to sample the analog signal, and make the back-end convert quality is almost the same as the front-end. This function can be operated by system maker and maintain the quality of display automatically, no manual operation is need.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of U.S. provisionalapplication titled “PHASE DETECT ALGORITHM USING FIRST ORDER SLOPE FORCLOCK RE-GENERATION” filed on Apr. 1, 2002, serial No. 60/369,527.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to signals processingtechnology in the application of display systems. More particular, thepresent invention relates to an apparatus and method of clock recoveryfor sampling analog signals provided to an analog-to-digital converter(ADC).

[0004] 2. Description of Related Art

[0005] Digital image processing is the most popular method used indisplay system. However, the drawback of digital signal processing isthe use of high bit counts while digital signals are transmitted betweendifferent systems. In addition, a great deal of bandwidth and processingpower are required for data transfer therebetween. Therefore, the use ofanalog signals is the prime solution in the application of datatransmission between different system interfaces. For example, eightdata lines are required for the transmission of a 8-bit digital pixelsignal of 256 colors, while one data line provided for the transmissionof analog signal is sufficient. Accordingly, the digital-to-analogconverter (DAC) and the analog-to-digital converter (ADC) have becomethe most important components for connecting two digital systems. Forexample, digital pixel data are generated by a graphics chip andconverted by the DAC into the associated analog pixel signals in acomputer. The analog pixel signals are transmitted, through a cable, tothe ADC of a back-end digital display device. The ADC receives theanalog pixel signals and converts them into the associated digital pixelsignals for image display. In other words, the ADC is used to generatethe digital pixel signals corresponding to the digital pixel data.

[0006] The analog pixel signals coming from a graphics system, such as apersonal computer (PC), are generated in synchronization with aninternal clock thereof. Therefore, it is required to provide a sampleclock with substantially the same frequency as that of the internalclock for analog signal processing at the back-end display device. Thequality of the image to be displayed on the back-end display is heavilyrelied upon whether the analog pixel signals are in synchronization withthe sample clock.

[0007] However, in the personal computer, no such sample clock will beso provided that the sample clock should be recovered from a referencesignal, such as a horizontal synchronization signal, hereinafter Hsync.The Hsync signal is provided with a time period which is Htt times thepixel clock period, wherein Htt designates the horizontal total pixelcounts for each line. Accordingly, the recovered clock should have afrequency of (Hsync frequency)×(Htt). However, Htt usually varies withdifferent display modes or even different graphic chips while performingat the same display mode. Therefore, mode detection is needed to assistthe display device to estimate the value of Htt. Conventionally, themode detection uses a clock with a fixed frequency to count the Hsyncsignal and to generate a count value. The count value can be employed tolook up the VESA (Video Electronic Standards Association) standard tableso as to obtain the possible display mode (XGA, SVGA, etc.). But theconventional method cannot calculate the exact Htt because the clockwith the fixed frequency is unrelated to the sample clock used by theback-end display device.

[0008] In addition, phase detection algorithm can be used for sampleclock recovery devicey by means of generating an estimated value of Httand then using the estimated value to approach the exact one. A sum ofΣ|pixel(n)−pixel(n+1)| is a simple way to implement the phase detectionalgorithm. However, the pixel difference method is useful for most kindsof patterns, but unfavorable for special patterns like block pattern,linear piece pattern, or the like. Moreover, the use ofΣ|pixel(n)−pixel(n+1)| cannot identify incorrect maxima and slopechange.

SUMMARY OF THE INVENTION

[0009] The present invention is a first-order-slope phase detectalgorithm for deducting the exact clock and phase. Analog signal isbasically a wave in the time domain, therefore the clock and phaseproblem can be solved in the mathematical way. For any curve f(x), thederivative of the curve f(x) in respect to time is f′(x), and f′(x)=0represents a local minimum or maximum. The local minima or maxima in thecurve must be some of the correct sample points. The phase detectalgorithm of the present invention is used to find the local minimum ormaximum points. We induce a slope polarity variation sum SPVS toindicate whether all local minimum and maximum points are actual partsof the sample points when a clock and phase is applied. The result ofcorrect sample clock will sample all local minimum and maximum pointsthat have maximum SPVS result because of curve transition f′(x)=0. As aresult, the SPVS value can accurately find the correct sample clock foran ADC. If all local minimum and maximum points are in the sets ofsample points, the total sum of SPVS will be the maximum. Also, theconcept of turning points, where the slope of the line changes fromeither positive or negative to zero, is introduced and applied toenhance the method of the present invention for special linear piecepatterns to make sure that no false result will be induced duringprocessing the SPVS. The present invention can detect all kinds ofpatterns includes the special pattern likes block, linear piece, and soon.

[0010] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTIOIN OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0012]FIG. 1 is a schematic diagram of a computer display systemaccording to a preferred embodiment of the present invention;

[0013]FIG. 2 is a detail block diagram of sample clock recovery deviceaccording to a preferred embodiment of the present invention;

[0014]FIG. 3 is an analog pixel signal having a block pattern;

[0015]FIG. 4 is a curve by sampling the analog pixel signal of FIG. 3according to a sample clock C;

[0016]FIG. 5 is a curve by sampling the analog pixel signal of FIG. 3according to a sample clock W;

[0017]FIG. 6 is an analog pixel signal having a linear piece pattern;

[0018]FIG. 7 is a drawing for explaining the concept of presentinvention; and

[0019]FIG. 8 is the flow chart according to one preferred embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020]FIG. 1 shows a computer display system. A computer graphic card100 generates Hsync, Vsync and pixel signals according to a sourceclock. A digital-to-analog converter (DAC) 102 is employed to convertdigital pixels data into analog pixel signals. A digital display device101 receives Hsync, Vsync, and the analog pixel signals through a cableconnected to the computer graphic card 100. A mode detector 103 uses aclock having a fixed frequency to count the Hsync and Vsync signals soas to obtain a total horizontal pixel number Htt and a total verticalline number Vtt. By referring to the VESA standard table, a rough Htt106 along with a display mode can be therefore generated in accordancewith the counted Htt. The rough Htt 106 is fed to the sample clockrecovery device 104 to generate a reference clock signal 107 to an ADC105 for sampling the analog pixel signals. The digital output of the ADC105 is then fed into sample clock recovery device 104 to determinewhether the sample data 108 are correct or not. If the sample data 108are incorrect, the sample clock recovery device 104 adjusts the periodand phase of the clock signal 107 to sample the analog pixel signalsagain. Such feedback processing continues again until the sample dataare correct.

[0021]FIG. 2 is a detailed block diagram of the sample clock recoverydevice 104. As shown in FIG. 2, the sample clock recovery device 104 hasa phase-locked loop (PLL) 201, an indicator 202, and a control 203. Thephase-locked loop 201 is used to lock the Hsync signal with a frequencyof FIN and generate the clock signal 107 with a frequency of FOUT by theratio FOUT=FIN×M/N, wherein M and N are integers. The indicator 202 isused to determine, responsive to the sample data 108, whether the sampledata 108 are prefect and to issue a detection result 204, accordingly.If the the sample data 108 is detected by the indicator 202 to beincorrect, the detection result 204 associated therewith is transmittedand sent to the control 203 so as to generate new values of M′ and N′via an output line 205. The phase-locked loop 201 receives the M′ andN′, and regenerates the clock signal 107 with another frequency FOUT′ of(FIN×M′/N′), accordingly. The clock signal 107 with FOUT′ is thereafterprovide for the ADC 105 to sample the analog pixel signals again. Asmentioned above, the regeneration/re-sampling feedback processingcontinues until the sample data 108 are determined to be correct.

[0022]FIG. 3 depicts the analog pixel signal having a block pattern 300.The block pattern may occur while two or more pixels are provided withthe same level. When two different sample clocks C and W are applied tothe block pattern 300, as referring to in FIGS. 4 and 5, the sample dataare described as follows:

[0023] Sample clock C: C_1=0, C_2=60, C_3=60, and C_4=0

[0024] Sample clock W: W_1=0, W_2=30, W_3=60, W_4=30, and W_5=0

[0025]FIG. 4 shows a fitting curve 400 by sampling the block pattern 300in accordance with the sample clock C. Thus, the result by using theconventional pixel differencemethod=|C_1−C_2|+|C_2−C_3|+|C_3−C_4|=60+0+60=120. FIG. 5 shows a fittingcurve 500 by sampling the block pattern 300 in accordance with thesample clock W. The result by using the conventional pixel differencemethod=|W_1−W_2|+|W_2−W_3|+|W_3−W_4|+|W_4−W_5|=30+30+30+30=120. As shownin FIGS. 4 and 5, even though the curve 400 should be better than thecurve 500, the conventional pixel difference method cannot differentiatebetween them.

[0026]FIG. 6 shows the analog pixel signal having a linear piece pattern600. For the same reason, the conventional pixel difference methodcannot differentiate the sample clock provided with better sample datafrom another sample clock with worse sample data, while both are appliedto the linear piece pattern 600.

[0027] According to the present invention, a slope-change approach isemployed. For a continuous curve f(x), the slope f′(x) is defined to bea “limit point” indicator. If f′(x)=0, x represents a local minimum ormaximum point which is designated to be a limit point). The limit pointhas a slope polarity changing from “positive” to “negative,” or from“negative” to “positive”. By taking the linear piece pattern 600 of FIG.6 as an example, the slope polarity at the sample point B, C, D, G, H,or I is changed from “positive” to “positive, or from “negative” to“negative”. Owing to occurrence of the limit point, the slope polarityat the sample point A, E, F, or J is changed from “zero” to “positive”,from “positive” to zero, from “zero” to “negative,” or from “negative”to “zero”. The point A, E, F, or J is defined to be “a turning point” inaccordance with the present invention. The turning points arecharacterized in that those points are provided with slope polaritychange. The more the sample point closes to the turning point, the morethe slope polarity changes.

[0028]FIG. 7 shows a drawing for explaining the concept of presentinvention. According to the present invention, if the sample pointslocated at the turning points the maximum slope-polarity-variation-sum(SPVS) can be obtained as compared to those far away from the turningpoints. The curve 700 is an analog signal, the curve 701 is the one thatthe sample points hit the turning points, and the curve 702 is the onethat the sample points miss the turning points. The SPVS of the curve701 is greater than that of the curve 702. Accordingly, the value ofSPVS is employed to generate the optimum sample clock.

[0029]FIG. 8 shows the flow chart of the SPVS method in accordance withone preferred embodiment of the present invention. The SPVS method ofthe present invention will be described step-by-step as follows:

[0030] (1) Step 801: Initially, SPVS is reset to be zero. Based on theestimated Htt 106 generated by the mode detector 103, a set of thecandidate clock signals is fed to the ADC 105. The sample data inresponse to different candidate clock signals are generated by the ADC105.

[0031] (2) Step 802: F′(n⁺)=F(n+1)−F(n) and F′(n⁻)=F(n)−F(n−1) aredefined and calculated for a sample point n, wherein F(n−1), F(n), andF(n+1) represent the sample data.

[0032] (3) Step 803: If F′(n⁺) and F′(n⁻) has no polarity change, thatis, from “positive” F′(n⁻) to “positive” F′(n⁺) or from “negative F′(n⁻)to negative F′(n⁺),” F(n) is determined not to be a turning point. Aftern is incremented by one, the flow goes back to Step 802. Otherwise, ifthe polarities of F′(n⁻) and F′(n⁺) are changed from “positive” to“negative,” from “positive” to zero, from zero to “positive,” from“negative” to “positive,” from “negative” to zero, or from zero to“negative,” the flow goes to Step 804. Where n=discrete sample points

[0033] n⁺=X>n X≈n

[0034] n⁻=X<n X≈n

[0035] (4) Step 804: the SPVS is accumulated according to Equation (1):

SPVS=SPVS+|F′(n⁺)−F(n⁻)|=|F(n+1)+F(n−1)−2F(n)|  (1)

[0036] (5) Step 805: By following Step 804, the flow goes to Step 805 tocheck whether all sample points has been done. If no, the flow goes backto Step 802 after n is incremented by one. If yes, the flow goes to Step806.

[0037] (6) Step 806: By comparing the SPVS values, the sample clockhaving the maximum SPVS is selected for sampling the analog pixelsignals.

[0038] If the SPVS method of the present invention is applied to theblock pattern of FIG. 3,

[0039] Clock C: C_1=0, C_2=60, C_3=60, C_4=0;

[0040] Clock W: W_1=0, W_2=30, W_3=60,W_4=30, W_5=0.

[0041] For clock C:

[0042] Turning points: C_1, C_2, C_3, and C_4 $\begin{matrix}{{SPVS} = {{{{F^{\prime}\left( {{C\_}1^{+}} \right)} - {F^{\prime}\left( {{C\_}1^{-}} \right)}}} + {{{F^{\prime}\left( {{C\_}2^{+}} \right)} - {F^{\prime}\left( {{C\_}2^{-}} \right)}}} + {{{F^{\prime}\left( {{C\_}3^{+}} \right)} - {F^{\prime}\left( {{C\_}3^{+}} \right)} - {F^{\prime}\left( {{C\_}3^{-}} \right)}}} + \quad {{{F^{\prime}\left( {{C\_}4^{+}} \right)} - {F^{\prime}\left( {{C\_}4^{-}} \right)}}}}} \\{= {{{{{C\_}0} + {{C\_}2} - {2{C\_}1}}} + {{{{C\_}1} + {{C\_}3} - {2{C\_}2}}} + {{{{C\_}2} + {{C\_}4} - {2{C\_}3}}} + {{{{C\_}3} + {{C\_}5} - {2{C\_}4}}}}} \\{= {60 + 60 + 60 + 60}} \\{= 240}\end{matrix}$

[0043] For clock W:

[0044] Turning points: W_1, W_3, W_5 $\begin{matrix}{{SPVS} = {{{{F^{\prime}\left( {{W\_}1^{+}} \right)} - {F^{\prime}\left( {{W\_}1^{-}} \right)}}} + {{{F^{\prime}\left( {{W\_}3^{+}} \right)} - {F^{\prime}\left( {{W\_}3^{-}} \right)}}} + {{{F^{\prime}\left( {{W\_}5^{+}} \right)} - {F^{\prime}\left( {{W\_}5^{-}} \right)}}}}} \\{{{= {{{{{W\_}0} + {{W\_}2} - {2{W\_}1}}} + \left. {{{W\_}2} + {{W\_}4} - {2{W\_}3}} \right)}}} + {{{{W\_}4} + {{W\_}6} - {2{W\_}5}}}} \\{= {30 + 60 + 30}} \\{= 120}\end{matrix}$

[0045] According to the SPVS method of the present invention, the sampleclock C, but not the sample clock W, is selected to correctly sample theanalog pixel signals due to its greater SPVS. The method of the presentinvention can accurately and easily calculate the correct sample clockfor the ADC 105 whereby greatly enhancing image quality and sharpness.

[0046] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. An apparatus for processing an analog signalalong with a synchronization signal, said apparatus comprising: a modedetector for generating a detected value in response to saidsynchronization; a clock recovery device for generating one clock signalin response to said detected value; and an analog-to-digital converterfor sampling said analog signal in response to said clock signal andgenerating sample data; wherein said sample data having at least oneturning point subject to slope polarity change are fed to said clockrecovery device for determining whether said sample data are eitherdesirable or undesirable, and said clock recovery device regeneratesanother clock signal in response to said undesirable sample data.
 2. Theapparatus as claimed in claim 1, wherein said clock recovery devicecomprises: a control for generating a control value in response to saiddetected value; a phase-locked loop for generating said one clock signalin response to said control value; and an indicator for generating adetection result to indicate whether said sample data are eitherdesirable or undesirable in response to said sample data; wherein saidcontrol updates said control value in response to said undesirablesample data, and thereafter said phase-locked loop regenerates saidanother clock signal in response to said updated control value.
 3. Theapparatus as claimed in claim 2, wherein said indicator generates saiddetection result by calculating a sum value of the slope polarity changeat said at least one turning point.
 4. The apparatus as claimed in claim3, wherein, near said at least one turning point n, from n⁻ to n⁺ issubject to said slope polarity change consisting of “+” to “−”, “+” to“0”, “0” to “+”, “−” to “+”, “−” to “0”, and “0” to “−”.
 5. Theapparatus as claimed in claim 4, wherein said sum value is defined to beΣ|f′(n⁺)−f′(n⁻)|, where f′(n⁺)=f(n+1)−f(n), f′(n⁻)=f(n)−f(n−1), and allof f(n+1), f(n), f(n−1) are selected from said sample data.
 6. Theapparatus as claimed in claim 5, said sum value of said desirable clocksignal should be maximized.
 7. A method for processing an analog signalalong with a synchronization signal, said method comprising thefollowing steps of: generating a detected value in response to saidsynchronization signal; generating one clock signal in response to saiddetected value; sampling said analog signal in response to said oneclock signal so as to generate sample data, wherein said sample data hasat least one turning point subject to slope polarity change; determiningwhether said sample data are either desirable or undesirable in responseto said slope polarity change; and regenerating another clock signal inresponse to said undesirable sample data.
 8. The method as claimed inclaim 7, further comprising: generating a control value in response tosaid detected value; generating said one clock signal in response tosaid control value; generating a detection result to indicate whethersaid sample data are either desirable or undesirable in response to saidsample data; and updating said control value in response to saidundesirable sample data regenerating said another clock signal inresponse to said updated control value.
 9. The method as claimed inclaim 8, wherein the step of generating said detection result isimplemented by calculating a sum value of the slope polarity change atsaid at least one turning point.
 10. The method as claimed in claim 9,wherein, near said at least one turning point n, from n⁻ to n⁺ issubject to said slope polarity change consisting of “+” to “−”, “+” to“0”, “0” to “+”, “−” to “+”, “−” to “0”, and “0” to “−”.
 11. The methodas claimed in claim 10, wherein said sum value is defined to beΣ|f′(n⁺)−f′(n⁻)|, where f′(n⁺)=f(n+1)−f(n), f′(n⁻)=f(n)−f(n−1), and allof f(n+1), f(n), f(n−1) are selected from said sample data.
 12. Theapparatus as claimed in claim 11, wherein said sum value of saiddesirable clock signal should be maximized.